(1) Field of the Invention
The present invention relates to the field of data storage. More specifically, the present invention relates to a method and apparatus for storing data in a plurality of latch-based memory elements.
(2) Art Background
When data must be transferred between two different time domains, it is often necessary to buffer the data temporarily before transferring it to the recipient time domain. This is usually accomplished by using a first-in first-out (FIFO) memory structure to queue the data until it is requested by recipient hardware.
When implemented in an application-specific integrated circuit (ASIC), a FIFO memory structure generally includes storage elements to store the data, address decode circuitry to select a specific one of the storage elements, and write-address generation circuitry for generating a sequence of write addresses at which the data is to be written. The size of the FIFO buffer is determined by the number and data-width of the individual storage elements and, above a certain buffer size, the storage elements are the dominant power and gate consuming logic element of the FIFO buffer.
Storage elements can be characterized by the manner in which they are triggered to store data. Flip-flops, also known as registers, are edge-triggered devices and are the storage element of choice in prior-art FIFO buffer designs. At each gating edge of a signal received at a clock enable input of the flip-flop, the signal present at the data input of the flip-flop is transferred to the flip-flop output. Since the output of a flip-flop can change state only at edges of the gating signal, any data setup and hold time requirements are centered around the gating edge. Since the gating signal is most commonly the clock signal used to indicate that a new data value is present, a new data value is stored in the flip-flop just before new data is asserted at the flip-flop input. As a result, system timing is kept simple, state transitions are deterministic, and race conditions that are otherwise difficult to detect and debug are avoided.
A transparent latch is another type of storage element that can be used in a FIFO buffer. Transparent latches, or "latches" for short, are enabled by a signal level rather than a signal edge. Instead of the clock enable input of a flip-flop, a transparent latch has a level-driven enable input. When an active-level signal is asserted at the latch enable input, the latch is "enabled", and data at the latch data input is passed through to the latch output. The effect is to make an enabled latch appear "transparent" from input to output, hence the term "transparent latch". Later, when the signal at the latch enable input transitions from the active level to an inactive level, the data present at the latch input is "latched" at the latch output.
The primary advantage of using latches as data storage elements instead of flip-flops is that latch-based storage elements use less power and require fewer equivalent gates than flip-flop-based storage elements. Reduced power consumption and gate count are particularly significant if the FIFO buffer is to be implemented in an ASIC.
The main disadvantage of using latch-based storage elements instead of flip-flop-based storage elements is that latches are more difficult to control than flip-flops. Setup and hold time requirements must be satisfied relative to a disabling edge of the latch enable signal which, in many designs, may be out of phase with the system clock signal. As a result, race conditions can arise between the hold time necessary to latch the data and a subsequent edge of the system clock which signals the next data value. If insufficient hold time is provided, the subsequent data value may be latched instead of the desired data value. Due to the hold time problems associated with latches, it is common to either relax the rate of data throughput to provide greater setup and hold time or to use flip-flops instead.
It would be desirable, therefore, to implement a sequentially written memory such as a FIFO buffer using transparent latches as the storage elements, but without having to reduce FIFO data throughput.